| 000 | 00719nam a2200217Ia 4500 | ||
|---|---|---|---|
| 005 | 20250131101651.0 | ||
| 008 | 210716s2009 xx 000 0 und d | ||
| 020 | _a9788184893397 | ||
| 040 | _cAIMIT LIBRARY | ||
| 041 | _aeng | ||
| 082 |
_a006.66 _21 _bVIJS |
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| 100 |
_aVijayaraghavan, Srikanth. _947786 |
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| 245 |
_aPractical guide for system verilog assertions / _cBy Srikanth Vijayaraghvan and Meyyappan Ramanathan. |
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| 250 | _a1st ed. | ||
| 260 |
_aNew Delhi : _bSpringer , _c2009. |
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| 300 |
_axxv,334p. ; _bPB _c22.8 cm. |
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| 650 |
_aSVS simulation methodology _947787 |
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| 650 |
_aSVA for protocol interface _9196528 |
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| 650 |
_aChecking the checker _9196529 |
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| 942 |
_2ddc _cBK _e1st _k006.66 VIJS |
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| 999 |
_c190229 _d190229 |
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