000 00523nam a2200157Ia 4500
008 210716s2008 xx 000 0 und d
020 _a9780070252219
041 _aeng
082 _a621.395 NAVZ
100 _aNavabi, Zainalabedin Navabi.
245 _aVerilog digital system design: rt level synthesis testbench and verification.
_bRt level synthesis testbench and verification.
250 _a2
260 _aNew Delhi
_bTata McGraw Hill Publishing Company Ltd
_c2008
300 _axvi,384
650 _aDigital Systems
999 _c189469
_d189469