Vijayaraghavan, Srikanth. <br/><br/>
Practical guide for system verilog assertions / 
By Srikanth Vijayaraghvan and Meyyappan Ramanathan. 
 - 1st ed. 
 - New Delhi :  Springer ,  2009. 
 - xxv,334p. ;  PB  22.8 cm. 
<br/><br/><label>ISBN: </label>9788184893397 
<br/><br/><label>Subjects--Topical Terms: </label><br/>SVS simulation methodology<br/>SVA for protocol interface<br/>Checking the checker
<br/><br/><label>Dewey Class. No.: </label>006.66   / VIJS